{"id":14394,"date":"2021-05-19T08:50:20","date_gmt":"2021-05-19T06:50:20","guid":{"rendered":"https:\/\/quantum.com.pl\/lauterbach-announces-the-support-for-siemenss-tessent-embedded-analytics\/"},"modified":"2021-05-19T11:31:48","modified_gmt":"2021-05-19T09:31:48","slug":"lauterbach-announces-the-support-for-siemenss-tessent-embedded-analytics","status":"publish","type":"post","link":"https:\/\/quantum.com.pl\/en\/lauterbach-announces-the-support-for-siemenss-tessent-embedded-analytics\/","title":{"rendered":"LAUTERBACH ANNOUNCES THE SUPPORT FOR SIEMENS&#8217;S TESSENT EMBEDDED ANALYTICS"},"content":{"rendered":"<p><strong>Debug Support for Tessent Embedded Analytics Infrastructure<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-14392 size-full\" src=\"https:\/\/quantum.com.pl\/wp-content\/uploads\/2021\/05\/LAUTERBACH-SIEMENS-TESSENT-EMBEDDED-ANALYTICS.jpg\" alt=\"\" width=\"800\" height=\"267\" srcset=\"https:\/\/quantum.com.pl\/wp-content\/uploads\/2021\/05\/LAUTERBACH-SIEMENS-TESSENT-EMBEDDED-ANALYTICS.jpg 800w, https:\/\/quantum.com.pl\/wp-content\/uploads\/2021\/05\/LAUTERBACH-SIEMENS-TESSENT-EMBEDDED-ANALYTICS-300x100.jpg 300w, https:\/\/quantum.com.pl\/wp-content\/uploads\/2021\/05\/LAUTERBACH-SIEMENS-TESSENT-EMBEDDED-ANALYTICS-768x256.jpg 768w, https:\/\/quantum.com.pl\/wp-content\/uploads\/2021\/05\/LAUTERBACH-SIEMENS-TESSENT-EMBEDDED-ANALYTICS-600x200.jpg 600w\" sizes=\"auto, (max-width: 800px) 100vw, 800px\" \/><\/p>\n<p>&nbsp;<\/p>\n<p>Lauterbach announces the support for Siemens Digital Industries Software\u2019s Tessent&#x2122; Embedded Analytics solution (the formerly known UltraSoC is now part of the Siemens Digital Industries Software). The current focus is on RISC-V and Arm\u00ae Cortex\u00ae cores but this can be extended to support additional architectures.<\/p>\n<p>SoCs are becoming increasingly complex and often contain cores from different manufacturers. The Tessent Embedded Analytics solution\u2019s open, manufacturer-independent, and modular design allows it to be tailored to support the debug and trace features of different IP blocks within an SoC. Indeed, Siemens provides the first core\u0002manufacturer independent IP block compliant to Efficient Trace for RISC-V Version 1 (program and data).<\/p>\n<p>Lauterbach, of course, provides support of the features of the Tessent Embedded Analytics IP and offers their customers the diverse set of features they have come to expect from the industry leader. For example: Classic debugging via JTAG or closed system debug via USB; RISC-V core trace analysis for single and multi-core devices; analysis of the SoC interconnect traffic; and off-chip trace via Arm CoreSight TPIU or HSSTP using the Tessent ATB interconnect.<\/p>\n<p>According to Norbert Weiss, Managing Director of Lauterbach GmbH, \u201cWith the support of Tessent Embedded Analytics, Lauterbach provides their customers with a powerful way to debug and trace their SoCs. The company ethos has been to always support the latest technologies in a timely fashion and provide the state-of-the-art debug and trace tools that our customers have come to expect.\u201d<\/p>\n<p>Richard Oxland, Product Manager for Siemens\u2019 Tessent Silicon Lifecycle Solutions group, said: \u201cWe have a longstanding commitment to empowering our customers to make the right choice for their designs \u2013 whether that\u2019s by supporting a broad range of core architectures, enabling the widest variety of approaches to debug, or cooperating with best-in-class tool vendors. We\u2019re delighted to be working with Lauterbach to provide our mutual customers with system-level insights, allowing them to harness SoC complexity and bring their products to market more quickly and at lower cost.\u201d<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Debug Support for Tessent Embedded Analytics Infrastructure &nbsp; &nbsp; Lauterbach announces the support for Siemens Digital Industries Software\u2019s Tessent&#x2122; Embedded Analytics solution (the formerly known UltraSoC is now part of the Siemens Digital Industries Software). The current focus is on RISC-V and Arm\u00ae Cortex\u00ae cores but this can be extended to support additional architectures. SoCs [&hellip;]<\/p>\n","protected":false},"author":6,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"inline_featured_image":false,"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"footnotes":""},"categories":[1653],"tags":[],"class_list":["post-14394","post","type-post","status-publish","format-standard","hentry","category-news-en"],"acf":[],"_links":{"self":[{"href":"https:\/\/quantum.com.pl\/en\/wp-json\/wp\/v2\/posts\/14394","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/quantum.com.pl\/en\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/quantum.com.pl\/en\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/quantum.com.pl\/en\/wp-json\/wp\/v2\/users\/6"}],"replies":[{"embeddable":true,"href":"https:\/\/quantum.com.pl\/en\/wp-json\/wp\/v2\/comments?post=14394"}],"version-history":[{"count":4,"href":"https:\/\/quantum.com.pl\/en\/wp-json\/wp\/v2\/posts\/14394\/revisions"}],"predecessor-version":[{"id":14398,"href":"https:\/\/quantum.com.pl\/en\/wp-json\/wp\/v2\/posts\/14394\/revisions\/14398"}],"wp:attachment":[{"href":"https:\/\/quantum.com.pl\/en\/wp-json\/wp\/v2\/media?parent=14394"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/quantum.com.pl\/en\/wp-json\/wp\/v2\/categories?post=14394"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/quantum.com.pl\/en\/wp-json\/wp\/v2\/tags?post=14394"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}