TRACE32 SUPPORTS SiFIVE’S RISC-V TRACE

Trace for SiFive’s RISC-V supported by Lauterbach’s TRACE32

 

 

Lauterbach is pleased to announce support for SiFive’s NEXUS IP trace for RISC-V processors. RISC-V is an Open Source Instruction Set Architecture which supports variable width instructions whilst allowing for the addition of custom instructions. TRACE32, of course, supports all 32 bit and 64 bit RISC-V cores and provides the capability to support custom instructions too.

The trace is based upon the IEEE-ISTO 5001 NEXUS trace standard and provides a way of non-intrusively emitting trace messages. The NEXUS 5001 standard is well defined and has been in use in many devices since its inception in 1999. The trace messages may contain information about program flow, or data accesses, or ownership messages and are sent to a ‘trace sink’. The SiFive implementation is independent of the trace infrastructure but defines interfaces to several types of trace sink, for example an SRAM sink or an Arm ATB (Advanced Trace Bus) sink which in turn leads to a trace port for spooling the data off-chip. These ports are also supported by TRACE32, allowing users to create a complete trace interface on their RISC-V implementations secure in the knowledge that industry leading tools will be available.